TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 92

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

TC5CR1<TC5S>
Internal source
clock
Counter
TTREG5
INTTMR5
interrupt
TC5OUT
3.9.3
3.
3.9
TC5CR2
<TC5SEL> = 0
fc/2
fc/2
fc/2
fc/2
Functional Description
TC5CR1<TFF5>=0
(1) 8-bit timer mode (TC5 and TC6)
11
7
5
3
The timer/counters 5 and 6 (TC5 and TC6) have the following five operating modes:
• 8-bit timer mode
• 8-bit pulse width modulation (PWM) output mode
• 16-bit timer mode
• 16-bit pulse width modulation (PWM) output mode
• 16-bit programmable pulse generation (PPG) mode
Each 16-bit mode is realized by cascading the timer/counters 5 and 6.
?
[Hz]
0
between the counter value and the timer register (TTREGj) value is detected, an
INTTMRj interrupt is generated and the counter is cleared. The counter then
continues counting up.
Source Clock
Table 3.9.4 Source Clock in 8-Bit Timer Mode (Internal Clock/TC5)
In the 8-bit timer mode, the counter counts up internal clock pulses. When a match
n
Note 1: In the 8-bit timer mode, do not change the TTREGj register value while the timer is running. In this
Note 2: j = 5, 6
TC5CR2
<TC5SEL> = 1
fs/2
−
−
−
1
Figure 3.9.4 8-Bit Timer Mode Timing Chart (TC5)
3
mode, the TTREGj does not have a shift register and the value written to the TTREGj is reflected
immediately after the write operation. Therefore, if the TTREGj value is changed while the timer is
running, unexpected operation may result.
[Hz]
2
3
fc = 27 MHz
Match detect
296.3 ns
75.9 µs
4.7 µs
1.2 µs
Figure 3.9.1Figure 3.9.2Figure 3.9.3
91CW40-90
n − 1 n 0
Resolution
表 3.9.1表 3.9.2表 3.9.3
fs = 32.768 kHz
244.14 µs
Counter clear
1
−
−
−
2
Match detect
fc = 27 MHz
302.2 µs
19.3 ms
75.6 µs
1.2 ms
Maximum Setting Time
n − 1
n 0
fs = 32.768 kHz
Counter clear
1
62.3 ms
−
−
−
2
TMP91CW40
2008-09-19
0