TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 72

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

3.7
(0340
TBTCR
Note: The divider output frequency (<DVOCK>, <DVSEL>) must be specified and the timing generator operating status
H
Divider Output (
approximately 50% duty pulses. This feature is useful for driving a piezoelectric beeper. Divider
output is implemented on the P72 (
)
The timing generator is provided with a divider output feature which enables output of
(<FCDIS>, <FSDIS>) must be changed while divider output is disabled (<DVOEN>=0).
Also note that the peripheral circuits using the timing generator (8-bit/16-bit timers) must also be stopped before changing
the <FCDIS> and <FSDIS> bits.
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Undefined value
Note 2: <DVSEL>=0 must not be set in SLOW and SLEEP modes.
Note 3: The TBTCR does not support read-modify-write operation.
DVOEN
DVOEN
DVOCK
FSDIS
FCDIS
7
Table 3.7.1 Divider Output Frequencies
6
Divider output enable/disable
Divider output (
frequency [Hz]
Timing generator control for
low-frequency clock (fs)
Timing generator control for
high-frequency control (fc)
DVOCK
DVOCK
00
01
10
11
DVO
5
Figure 3.7.1 Divider Output Control Register
)
DVO
DVSEL
4
pin)
DVSEL = 0
13.184 k
26.367 k
3.296 k
6.592 k
―
3
DVO
91CW40-70
Divider Output Frequency [Hz]
0: Disable output
1: Enable output
00
01
10
11
0: Operate
1: Stop
0: Operate
1: Stop
) pin.
―
2
FSDIS
DVSEL = 0
(at fc = 27.0 MHz, fs = 32.768 kHz)
1
fc/2
fc/2
fc/2
fc/2
13
12
11
10
FCDIS
DVSEL = 1
0
1.024 k
2.048 k
4.096 k
8.192 k
(Initial value:0000 **00)
DVSEL = 1
fs/2
fs/2
fs/2
fs/2
5
4
3
2
TMP91CW40
2008-09-19
W
R/W