TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 193

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

3.17.3
Control Registers
Note1: If the disable control is used, set the disable code (B1H) to WDCR after writing the clear code (4EH) once.
Note2: If the watchdog timer setting is changed, change setting after setting to disable condition once.
(2) Watchdog timer control register (WDCR)
(1) Watchdog timer mode register (WDMOD)
The watchdog timer is controlled by two registers called WDMOD and WDCR.
(Please refer to setting example.)
•
•
•
c.
binary counter.
a. Time-out period <WDTP1:0>
b. Watchdog timer enable/disable control <WDTE>
This register is used to disable the watchdog timer and to clear the watchdog timer’s
it reaches the time-out time. A reset initializes WDMOD<RESCR> = 0 so that a
time-out does not cause a system reset.
Disabling the watchdog timer
Enabling the watchdog timer
Clearing the watchdog timer counter
writing the disable code (B1H) to the WDCR register.
causes the counter to start counting again.
WDCR
WDMOD
WDCR
WDCR
A reset initializes WDMOD<WDTP1:0> to 00. Figure 3.17.4 shows possible
time-out periods.
disable the watchdog timer, the clearing of the <WDTE> bit must be followed by a
write of a special key code (B1H) to the WDCR register. This protects the watchdog
timer from being inadvertently disabled. To re-enable the watchdog timer, it is
only necessary to set the <WDTE> bit to 1.
System reset <RESCR>
The watchdog timer can be disabled by clearing WDMOD<WDTE> to 0 and then
The watchdog timer can be enabled by setting WDMOD<WDTE> to 1.
Writing the clear code (4EH) to the WDCR register clears the binary counter and
This bit is used to program the watchdog timer to generate a system reset when
A reset initializes WDMOD<WDTE> to 1, enabling the watchdog timer. To
This 2-bit field determines the duration of the watchdog timer time-out interval.
← 0 1 0 0 1 1 1 0
← 0 − − X X − − 0
← 1 0 1 1 0 0 0 1
← 0 1 0 0 1 1 1 0
91CW40-191
Write the clear code (4EH).
Clear <WDTE> to 0.
Write the disable code (B1H).
Write the clear code (4EH).
TMP91CW40
2008-09-19