TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 125

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

Timing to write
transmission data
SCLK0 output
(<SCLKS>=0
Rising edge mode)
<ITX0C>
(INTTX0
Interrupt request)
SCLK0 output
(<SCLKS>=1
Falling edge mode)
TXD0
(INTTX0 interrupt request)
SCLK0 input
(<SCLKS> = 0
rising edge mode)
SCLK0 入力
(<SCLKS> = 1
falling edge mode)
TXD0
<ITX0C>
a.
Figure 3.10.16 Transmit Operation in I/O Interface Mode (SCLK output mode)
Figure 3.10.17 Transmit Operation in I/O Interface Mode (SCLK0 input mode)
Transmit operations
the SCLK input is activated. The 8 bits of a character in the transmit buffer are shifted
out on the TXD0 pin, synchronous to the programmed edge of the SCLK0 input. When
all the bits have been shifted out, the INTES0<ITX0C> is set and the transmit-done
interrupt (INTTX0) is generated.
the eight bits of the character are shifted out on the TXD0 pin and the
synchronization clock is driven out from the SCLK pin. When all the bits have been
shifted out, the INTES0<ITX0C> is set and the transmit-done interrupt (INTTX0) is
generated.
In SCLK output mode, each time the CPU writes a character to the transmit buffer,
In SCLK input mode, the CPU must write a character to the transmit buffer before
Bit0
Bit0
91CW40-123
Bit1
Bit1
Bit5
Bit6
Bit6
Bit7
Bit7
TMP91CW40
2008-09-19
(Internal clock
timing)