TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 189

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

Table 3.16.3 Relationships between Analog Input Channels and AD Conversion Result Registers
(5) Conversion time
(6) Storing and reading AD conversion results
= 27 MHz).
(ADREG04H/L to ADREG37H/L). These registers are read only.
goes into the ADREG04H/L to ADREG37H/L sequentially. In other modes, conversion
results in channels AN0, AN1, AN2 and AN3 are stored in the ADREG04H/L,
ADREG15H/L, ADREG26H/L and ADREG37H/L respectively.
conversion result register has been read. This bit is set when the conversion result is
loaded into the ADREGxH/ADREGxL register pair, and cleared when either the
ADREGxH or ADREGxL is read.
conversion result registers.
Reading the conversion result also clears the conversion end flag (ADMOD0<EOCF>).
Table 3.16.3 shows the relationships between the analog input channels and the AD
Analog Input Channel
The conversion process requires 84 conversion states per channel (6.2 μs when f
AD conversion results are stored in the conversion result high/low register pairs
In fixed-channel continuous conversion mode with <ITM0> set to 1, conversion data
Bit0 (<ADRxRF>) in each ADREGxL register indicates whether or not the
(Port 5)
AN0
AN1
AN2
AN3
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
91CW40-187
Other Modes
AD Conversion Result Registers
Conversion Mode (<ITM0>=1)
Fixed-Channel Continuous
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
TMP91CW40
2008-09-19
FPH