TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 81

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

ECIN1 pin input
Internal clock
Counter
INTTMR1 interrupt
Program
ECIN1 pin input
INTTMR1 interrupt
a) When the timer is started with ECIN1 pin at low level
Note 1:
Note 2:
Timer
start
(3) Pulse width measurement mode
the AND pulse of the ECIN1 pin input (window pulse) and the internal clock. The
internal clock is selected by TC1CR1<TC1CK>. An INTTMR1 interrupt is generated at
the falling edge or at both the rising and falling edges of the window pulse, as
programmed in TC1CR2<SGEDG>. The counter value (TREG1A) should be read in the
interrupt service routine while the counter is stopped (i.e., ECIN1 pin is at low level).
Then, the counter should be cleared by using TC1CR<TC1C>. If the counter is not
cleared, it resumes counting up from the current value when counting is started again.
When the TREG1A counts up from FFFFH to 0000H
not an overflow occurred can be monitored by TC1SR <HEOVF>. The overflow flag
state is retained until the counter is cleared.
INTTMR1 interrupt generation timing when TC1CR2<SGEDG> = 1 (falling and rising edges) in the pulse width
measurement mode
In the pulse width measurement mode, the operation status monitor (TC1SR<HECF>) cannot be used.
In the pulse width measurement mode, the counter counts up on the rising edge of
Timer
start
Figure 3.8.6 Pulse Width Measurement Mode Timing Chart
0
Count
start
↓
1
2
3
91CW40-79
n − 2
n − 1
Count
stop
b) When the timer is started with ECIN1 pin at high level
Interrupt service routine
Timer
start
↓
n
,
Read & clear
When an ECIN1 port started a timer at
the time of “1”, the interrupt just after the
start does not occur.
an overflow occurs. Whether or
0
Count
start
TMP91CW40
2008-09-19
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