TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 200

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TMP91xy40FG

Manufacturer Part Number
TMP91xy40FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy40FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/F
Rom Combinations
128
Ram Combinations
4
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
4
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
3
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
61
Power Supply Voltage(v)
2.2 to 3.6
4.5
4.6
Note 1: Xc represents the cycle period of the high-frequency oscillator clock (fc).
Note 2: In the above table, the letter x represents the f FPH cycle period, which is half the system clock (f SYS ) cycle period used in
Low pulse width for
High pulse width for
Timer/counter input
(ECIN1 to ECIN3 input)
Parameter
Timer/Counter Input (ECIN) Characteristics
Interrupts
(1)
the CPU core. The f FPH cycle period varies depending on the clock gear setting and whether the high-frequency or low
frequency oscillator is used.
Parameter
NMI
, INT0 and INT1 interrupts
NMI
NMI
, INT0, INT1
, INT0, INT1
Symbol
t
TC1
Frequency
measurement mode
VDD =2.7 to 3.6 V
Frequency
measurement mode
VDD =2.2 to 2.7 V
Symbol
t
t
INTAH
INTAL
4X + 40
4X + 40
Min
Equation
91CW40-198
Condition
Max
Count on a single edge
Count on both edges
Count on a single edge
Count on both edges
290
290
Min
16 MHz
Max
Min
188
188
Min
27 MHz
Typ.
Max
(fc/2 = max. 8MHz)
Max
fc/2
TMP91CW40
Unit
ns
ns
2008-09-19
MHz
Unit

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