TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 184

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

ADREG15H
ADREG04L
ADREG15L
ADREG04H
(02A3H)
(02A0H)
(02A2H)
(02A1H)
Channel x conversion
result bits
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Lower 2 bits of an AD
Lower 2 bits of an AD
ADR01
ADR09
ADR11
ADR19
conversion result
conversion result
7
7
7
7
Undefined
Undefined
R
R
ADREGxH
Figure 3.16.4 AD Conversion Registers (3)
9
ADR00
ADR08
ADR10
ADR18
7
6
6
6
6
AD Conversion Result High Register 0/4
8
AD Conversion Result Low Register 0/4
AD Conversion Result Low Register 1/5
AD Conversion Result High Register1/5
6
7
5
ADR07
ADR17
4
5
5
Upper 8 bits of an AD conversion result
5
5
Upper 8 bits of an AD conversion result
6
91CW40-182
3
5
2
ADR06
ADR16
4
•
•
4
4
4
4
1
Undefined
Undefined
Bits 5 to 1 are always read as 1.
Bit0 (<ADRxRF>), when set, indicates that the conversion
result has been stored in the ADREGxH/L register pair.
This bit is cleared when either the ADREGxH or
ADREGxL is read.
3
0
R
R
2
ADR05
ADR15
3
3
3
3
1
7
0
6
ADR04
ADR14
5
2
2
2
2
4
3
ADR03
ADR13
2
1
1
1
1
ADREGxL
1
0
Conversion
result store
flag
1: Stored
Conversion
result store
flag
1: Stored
TMP91CW40
ADR0RF
ADR1RF
ADR02
ADR12
2008-09-19
0
R
0
0
R
0
0
0