TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 80

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

TREG1A
INTTMR1 interrupt
ECIN1 pin input
Counter
* Before changing the TC1CR2<TC1SEL>, TC1CR1<TC1M> and TREG1A, be sure to once change the source clock to an
internal clock.
Programming sequences (Be sure to follow these sequences.)
•
•
(2) Event counter mode
LD
LD
LDW (TREG1A),0100H
LD
LD
LD
LD
LDW (TREG1A),0080H
LD
LD
0
Setting initial values
Changing the timer register contents (after the timer is started)
input. When a match between the counter value and the TREG1A register value is
detected, an INTTMR1 interrupt is generated and the counter is cleared. Then, the
counter continues counting up on each rising edge of the ECIN1 pin input. The
maximum allowed frequency is fc/2
(in SLOW or SLEEP mode) when TC1CR2<SEG>=0. Both high and low levels require
a pulse width of at least two machine cycles.
Start
In the event counter mode, the counter counts up on the rising edge of the ECIN1 pin
(TC1CR1),9CH
(TC1CR1),80H
(TC1CR1),9CH
(TC1CR1),0DCH
(TC1CR2),00H
(TC1CR1),80H
(TC1CR1),9CH
(TC1CR1),0DCH
n
Figure 3.8.5 Event Counter Mode Timing Chart
1
: Stop the timer & clear the counter.
: Set the source clock to an internal clock once.
: Set the timer register. (TREG1AH=00H, TREG1AL=80H)
: Change the source clock to the ECIN1 pin input.
: Start the timer.
: Set the <TC1SEL> bit. (<TC1SEL>=0)
: Select the event counter mode.
: Set the timer register. (TREG1AH=01H, TREG1AL=00H)
: Set the source clock to the ECIN1 pin input.
: Start the timer.
2
<SEG>=0 to count up on the rising edge of ECIN1
91CW40-78
4
[Hz] (in NORMAL or IDLE2 mode) and f/2
Match detect
n − 1
n
0
Counter clear
1
2
TMP91CW40
2008-09-19
4
[Hz]