TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 194

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

Read-modify-
write instructions
cannot be used.
(0301H)
WDCR
WDMOD
(0300H)
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
WDT
control
0: Disable
1: Enable
WDTE
R/W
7
1
7
Figure 3.17.5 Watchdog Timer Control Register
Figure 3.17.4 Watchdog Timer Mode Register
Select detecting time
00: 2
01: 2
10: 2
11: 2
Watchdog timer detection time
WDTP1
System Clock
<SYSCK>
SYSCR1
6
6
15
17
19
21
0
/f
/f
/f
/f
1 (fs)
0 (fc)
SYS
SYS
SYS
SYS
R/W
WDTP0
91CW40-192
5
5
0
2.0
2.43 ms
B1H: WDT disable code
4EH: WDT clear code
Always
write 0.
00
R/W
4
s
4
−
0
W
−
−
Watchdog Timer Detection Time
Always
write 0.
Watchdog timer enable
Watchdog timer out control
IDLE2 control
R/W
3
0
1
0
1
0
1
3
−
0
8.0
9.71 ms
Other
WDMOD<WDTP1:0>
B1H
4EH
01
−
Internally route the WDT time-out signal to
the system reset.
Stop
Operation
Disable
Enable
Special code
s
IDLE2
0: Stop
1: Operate
I2WDT
2
Disable code
Clear code
−
2
0
32.0
38.84 ms
at fc = 27 MHz, fs = 32.768 kHz
R/W
10
1:Internally
RESCR
connects
WDT out
to the
reset pin
1
s
1
0
TMP91CW40
2008-09-19
Always
write 0 .
128.0
155.34 ms
0
R/W
11
0
−
0
s