TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 116

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

(6) Receive buffer
(7) Transmit counter
(8) Transmit controller
TXDCLK
SIOCLK
serially shifted bit by bit into receive buffer 1. When a whole character (i.e., 7 or 8 bits,
as programmed) is loaded into receive buffer 1, it is transferred to receive buffer 2
(SC0BUF), and the receive-done interrupt (INTRX0) is generated.
start accepting a new character before the CPU picks up the previous character in
receive buffer 2. However, the CPU must read receive buffer 2 before receive buffer 1 is
filled with a new character; otherwise, an overrun error occurs, causing the character
previously in receive buffer 1 to be lost. Even in that case, the contents of receive buffer
2 and the SC0CR<RB8> bit are preserved.
most-significant bit in 9-bit UART mode.
in a multidrop system to wake up whenever an address character is received. Setting
the SC0MOD0<WU> bit to 1 enables the wakeup feature. When the SC0CR<RB8> bit
has received an address/data flag bit set to 1, the receiver generates the INTRX
interrupt.
receive counter, the transmit counter is also clocked by SIOCLK. The transmitter
generates a transmit clock (TXDCLK) pulse every 16 SIOCLK pulses.
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The receive buffer is double-buffered to prevent overrun errors. Received data is
The CPU reads a character from receive buffer 2 (SC0BUF). Receive buffer 1 can
The SC0CR<RB8> bit holds the parity bit in 8-bit UART mode with parity and the
In 9-bit UART mode, the slave controller wakeup feature allows the slave controller
The transmit counter is a 4-bit binary up counter used in UART mode. Like the
I/O interface mode
UART mode
the transmit controller shifts out each bit in the transmit buffer to the TXD0 pin at
the rising or falling edge of the shift clock driven out on the SCLK0 pin.
to 1, the transmit controller shift out each bit in the transmit buffer to the TXD0
pin at the rising or falling edge of the SCLK input, as programmed in the
SC0CR<SCLKS> bit.
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begins transmission at the next rising edge of TXDCLK, producing a transmit
shift clock (TXDSFT).
When the SCLK pin is configured as an output by clearing the SC0CR<IOC> to 0,
When the SCLK0 pin is configured as an input by setting the SC0CR<IOC> bit
Once the CPU loads a character into the transmit buffer, the transmit controller
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Figure 3.10.6 Transmit Clock Generation
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TMP91CW40
2008-09-19
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