TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 42

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

DMA0V
DMA1V
DMA2V
DMA3V
Symbol
Symbol
DMAR
DMAB
DMA0
start vector
DMA1
start vector
DMA2
start vector
DMA3
start vector
DMA
software
request
register
DMA
burst
register
Name
Name
(4) Micro DMA start vector registers
(5) Micro DMA burst specification
micro DMA processing. The interrupt source having the micro DMA start vector
specified in this register is assigned as a micro DMA request source.
a request from the CPU and generates a micro DMA transfer complete interrupt for the
relevant channel. Then, the CPU clears the micro DMA start vector register, thus
clearing the micro DMA request source for the channel. If it is necessary to continue
micro DMA processing, the micro DMA start vector register must be set again in the
service routine for the micro DMA transfer complete interrupt.
time, the channel having the smallest number takes precedence. Therefore, if the same
vector is set in the micro DMA start vector registers of two channels, micro DMA
transfer is first performed with the smaller-numbered channel until it completes.
Unless the interrupt controller reloads the micro DMA start vector for this channel,
micro DMA transfer is then performed with the larger-numbered channel (micro DMA
chaining).
can cause transfer to continue until the transfer counter register reaches zero. Burst
transfer can be specified by setting the DMAB register bit corresponding to each micro
DMA channel to 1.
A micro DMA start vector register specifies which interrupt source is assigned to
When the micro DMA transfer counter reaches zero, the interrupt controller receives
If the same vector is set in two or more micro DMA start vector registers at the same
The micro DMA supports burst specification, with which a single micro DMA startup
are prohibited)
modify-write
instructions
Address
Address
(Read-
8AH
80H
81H
82H
83H
89H
7
7
6
6
91CW40-40
DMA0V5
DMA1V5
DMA2V5
DMA3V5
5
0
0
0
0
5
DMA0V4
DMA1V4
DMA2V4
DMA3V4
4
0
0
0
0
4
DMA0V3
DMA1V3
DMA2V3
DMA3V3
DMAR3
DMAB3
DMA0 start vector
DMA1 start vector
DMA2 start vector
DMA3 start vector
3
0
0
0
0
3
0
0
R/W
R/W
R/W
R/W
DMA0V2
DMA1V2
DMA2V2
DMA3V2
1: DMA burst request
DMAR2
1: DMA soft request
DMAB2
2
0
0
0
0
2
0
0
R/W
R/W
DMA0V1
DMA1V1
DMA2V1
DMA3V1
DMAR1
DMAB1
1
1
TMP91CW40
0
0
0
0
0
0
2008-09-19
DMA0V0
DMA1V0
DMA2V0
DMA3V0
DMAR0
DMAB0
0
0
0
0
0
0
0
0