TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 62

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

ODE
(002FH)
PA
(001EH)
PACR
(0020H)
PAFC
(0021H)
Note 1: The PACR and PAFC do not support
Note 2: To specify the TXD pin as an open-drain
read-modify-write operation.
output, write 1 to bit 6 (for the TXD2 pin)
or bit 7 (for the TXD3 pin). The
PA1/RXD2 and PA4/RXD3 pins do not
have a register bit for selecting the port
or SIO function. The input to these pins
is always directed to the SIO as serial
receive data even when the pins are
used as general-purpose input pins.
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
PA3
open-drain
output
0: Disable
1: Enable
ODEA3
7
7
7
7
0
PA0
open-drain
output
0: Disable
1: Enable
ODEA0
6
6
6
6
0
Figure 3.5.18 Port A Registers
0: Port
1: SCLK3
P93
open-drain
output
0: Disable
1: Enable
ODE93
output
PA5C
PA5F
PA5
Port A Function Register
W
Port A Control Register
5
5
5
5
0
0
0
Open-Drain Register
91CW40-60
Port A Register
Data from external port (Output latch register is set to 1.)
P90
open-drain
output
0: Disable
1: Enable
ODE90
PA4C
PA4
4
4
4
4
0
0
R/W
0: Input
0: Port
1: TXD3
P83
open-drain
output
0: Disable
1: Enable
ODE83
PA3C
PA3F
PA3
W
3
3
3
3
0
0
0
R/W
W
0: Port
1: SCLK2
P82
open-drain
output
0: Disable
1: Enable
ODE82
output
PA2C
1: Output
PA2F
PA2
W
2
2
2
2
0
0
0
Open-drain output setting
PA0 TXD2 output setting
PA2 SCLK2 output setting
PA3 TXD3 output setting
PA5 SCLK3 output setting
P81
open-drain
output
0: Disable
1: Enable
0 Disable
1 Enable
PAFC<PA0F>
PACR<PA0C>
PAFC<PA2F>
PACR<PA2C>
PAFC<PA3F>
PACR<PA3C>
PAFC<PA5F>
PACR<PA5C>
ODE81
PA1C
Port A input/output setting
PA1
0 Input
1 Output
1
1
1
1
0
0
0: Port
1: TXD2
P80
open-drain
output
0: Disable
1: Enable
ODE80
PA0C
TMP91CW40
PA0F
PA0
W
0
0
0
0
0
0
0
2008-09-19
1
1
1
1
1
1
1
1