TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 199

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TMP91xy40FG

Manufacturer Part Number
TMP91xy40FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy40FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/F
Rom Combinations
128
Ram Combinations
4
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
4
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
3
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
61
Power Supply Voltage(v)
2.2 to 3.6
4.4
Note 1:
Note 2:
Note 3:
SCLK period
Output Data
SCLK rising
/falling edge*
SCLK rising
/falling edge*
SCLK rising
/falling edge*
Valid data input
/falling edge*
SCLK period
Output Data
SCLK rising
/falling edge*
SCLK rising
/falling edge*
SCLK rising
/falling edge*
Valid data input
/falling edge*
(input falling mode)
Output mode/
input rising mode
SIO Timing (I/O Interface Mode)
(1) SCLK input mode
(2) SCLK output mode
SCLK rise or fall: Measured relative to the programmed active edge of SCLK.
The values shown in the 27 MHz and 16 MHz columns are measured with t
In the above tables, the letter x represents the f FPH cycle period, which is half the system clock (f SYS ) cycle period used in
the CPU core. The f FPH cycle period varies depending on the clock gear setting and whether the high-frequency or low
frequency oscillator is used.
Output data
Input data
Parameter
Parameter
SCLK
SCLK
→ Output Data hold
→ Input Data hold
→ Valid Data hold
RXD
TXD
→ SCLK rising
→ Output Data hold
→ Input Data hold
→ Valid Data hold
→ SCLK rising
SCLK rising
/falling edge*
SCLK rising
/falling edge*
/falling edge*
/falling edge*
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
OSS
OHS
HSR
SRD
RDS
OHS
SCY
SCY
OSS
HSR
SRD
RDS
(V
(V
t
t
t
SCY
SCY
OSS
t
t
1X + 180
SCY
CC
SCY
CC
t
SCY
16X
Min
/2 − 40
/2 − 40
t
= 2.7V to 3.6V)
Valid
0
= 2.2V to 2.7V)
SCY
/2 − 4X − 110
/2 − 4X − 180
91CW40-197
3X + 10
0
0
/2 + 2X + 0
16X
Min
0
t
Equation
OHS
Equation
t
SRD
t
SCY
8192X
− 1X − 180
Max
t
SCY
t
RDS
Valid
Max
1
1
− 0
Min
460
460
243
1.0
Min
140
625
198
1.0
0
70
16 MHz
t
0
HSR
16 MHz
SCY
= 16X.
Max
512
757
1000
Max
Valid
2
2
0.59
Min
256
256
217
0.59
Min
370
121
38
0
0
27 MHz
27 MHz
Max
592
Max
303
375
Valid
Unit
μs
ns
ns
ns
ns
ns
Unit
TMP91CW40
3
3
μs
ns
ns
ns
ns
ns
2008-09-19

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