TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 43

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

(6) Precautions
Note: The following instructions or pin state transition are equivalent to an instruction that clears an interrupt request
When INT0 or INT1 is set
as a level-sensitive
interrupt
INTRX
independently. Therefore, after accepting an interrupt the CPU may fetch an
instruction that clears the interrupt request flag for this interrupt
before the interrupt is about to be generated. In this case, the CPU may execute this
interrupt request clear instruction after accepting the interrupt request but before
reading the interrupt vector for this interrupt. If this happens, the CPU reads “0008H”
(interrupt vector cleared) and reads the interrupt vector from address FFFF08H.
instruction for clearing an interrupt request flag. After the clear instruction is
executed, at least one instruction must be inserted before the EI instruction is executed
to re-enable interrupts.(e.g., “NOP” × 1 times) If the EI instruction immediately
follows the clear instruction, interrupts may be enabled before the interrupt flag is
cleared.
bits of the status register SR), the DI instruction must be executed to disable
interrupts before executing the POP SR instruction.
attention:
flag:
INT0/INT1: Instruction that changes the pin mode to level-sensitive after an interrupt is generated in
INTRX:
The instruction execution unit and the bus interface unit of this CPU operate
To avoid the above situation, make sure to execute the DI instruction before an
When the POP SR instruction is used to modify the interrupt mask level (<IFF2:0>
In addition, note the following two exceptional circuits which demand special
edge-triggered mode.
Change in the pin input level (from high to low) after an interrupt request is generated in level-sensitive
mode
Instruction that reads the receive buffer.
interrupt response sequence, INT0 must be held high until the
interrupt response sequence is completed. When level-sensitive INT0
is used to exit HALT mode, INT0 must also be held high once it is
driven from low to high until HALT mode is exited. (Ensure that it is not
temporarily driven low due to noise during that period.)
interrupt request flag accepted in level-sensitive mode is not cleared.
Use the following sequence to clear the interrupt request flag:
reading the serial channel receive buffer. It cannot be cleared by an
instruction.
than edge-triggered), the interrupt request flip-flop is disabled so that
a peripheral interrupt request directly passes through the S input of
the flip-flop to appear at the Q output. Changing the mode (edge to
level) causes the previous interrupt request flag to be cleared
automatically.
When INT0 or INT1 is used as a level-sensitive interrupt pin (rather
If INT0 is driven from low to high causing the CPU to start an
When INT0 is changed from level-sensitive to edge-triggered, any
Clearing the interrupt request flip-flop requires a system reset or
DI
LD (IIMC), 00H
LD (INTCLR), 0AH ; Clear INT0 interrupt request flag.
NOP
EI
91CW40-41
; Change from level to edge.
; Wait EI instruction.
(Note)
TMP91CW40
immediately
2008-09-19