TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 119

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

(12) Signal generation timing
Note: In 9 data bits and 8 data bits with parity mode, interrupts coincide with the ninth bit pulse. Thus, when an
2.
3.
a.
Receive operation
Transmit operation
b.
Interrupt timing
Framing error timing
Parity error timing
Overrun error timing
Interrupt timing
Transmit
interrupt timing
Receive
interrupt timing
Parity error <PERR>
Framing error <FERR>
UART mode
I/O interface mode
interrupt occurs, it is necessary to wait for a 1-bit period (to allow the stop bit to be transferred) before
checking for a framing error.
the RXD pin does not match the expected parity computed from the character
transferred to receive buffer 2 (SC0BUF).
(The middle three of the 16 samples are used to determine the bit value.)
A parity error is reported when the parity bit attached to a character received on
A framing error is reported when a 0 is detected where a stop bit was expected.
Mode
Mode
SCLK output mode
SCLK input mode
SCLK output mode
SCLK input mode
Middle of the last bit
(bit 8)
Middle of the last bit
(bit 8)
Middle of the stop bit
Immediately before
the stop bit is shifted
out
9 Data Bits
9 Data Bits
91CW40-117
―
Immediately after the last bit data.
(See Figure 3.10.16)
Immediately after the rising or falling edge of the last SCLK pulse,
as programmed. (See Figure 3.10.17)
When a received character has been transferred to receive buffer 2
(SC0BUF) (i.e. immediately after the last SCLK pulse)
(See Figure 3.10.18)
When a received character has been transferred to receive buffer 2
(SC0BUF) (i.e. immediately after the last SCLK pulse)
(See Figure 3.10.19)
Middle of the last bit
(parity bit)
Middle of the last bit
(parity bit)
Middle of the stop bit
Middle of the last bit
(parity bit)
Immediately before the
stop bit is shifted out
8 Data Bits with Parity
8 Data Bits with Parity
Middle of the stop bit
Middle of the stop bit
Middle of the stop bit
Middle of the stop bit
Immediately before the stop bit
is shifted out
8 Data Bits with No Parity
7 Data Bits with No Parity
8 Data Bits with No Parity
7 Data Bits with No Parity
7 Data Bits with Parity
7 Data Bits with Parity
TMP91CW40
2008-09-19