mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 165

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

8.6.3.1
The MPR specifies the access privilege level associated with each bus master in the platform. The register
provides one bit per bus master, where bit 3 corresponds to master 3 (Fast Ethernet Controller, not used on
MCF5216 and MCF5214), bit 2 to master 2 (DMA Controller), bit 1 to master 1 (internal bus master), and
bit 0 to master 0 (ColdFire core).
Only trusted bus masters can modify the access control registers. If a non-trusted bus master attempts to
write any of the SACU control registers, the access is aborted with an error termination and the registers
remain unaffected.
The processor core is connected to bus master 0 and is always treated as a trusted bus master. Accordingly,
MPR[0] is forced to 1 at reset.
8.6.3.2
Access to several on-chip peripherals is controlled by shared peripheral access control registers. A single
PACR defines the access level for each of the two modules. These modules only support operand reads
Freescale Semiconductor
IPSBA
0x03C
0x020
0x024
0x028
0x030
0x034
0x038
Offset
0x02c
R
Bits Name
7–4
3–0
Master Privilege Register (MPR)
Peripheral Access Control Registers (PACR0–PACR8)
[31:28]
MPR
—
Address
GPACR0
PACR0
PACR4
PACR7
MPR
Reset
Field
—
—
—
R/W
Reserved. Should be cleared.
Each 1-bit field defines the access privilege level of the given bus master n.
0 All bus master accesses are in user mode.
1 All bus master accesses use the sourced user/supervisor attribute.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
[27:24]
7
Figure 8-8. Master Privilege Register (MPR)
Table 8-7. SACU Register Memory Map
Table 8-8. MPR[n] Field Descriptions
[23:20]
—
—
GPACR1
PACR1
—
—
—
—
—
[19:16]
IPSBAR + 0x020
—
0000_0011
Description
R/W
[15:12]
—
PACR2
PACR5
PACR8
MPR[3:0]
—
—
—
—
[11:8]
—
System Control Module (SCM)
0
[7:4]
—
PACR3
PACR6
—
—
—
—
—
[3:0]
—
8-13