mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 399

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

21.2.4
As part of the output-compare function, each DTRRn contains the reference value compared with the
respective free-running timer counter (DTCNn).
The reference value is matched when DTCNn equals DTRRn. The prescaler indicates that DTCNn should
be incremented again. Therefore, the reference register is matched after DTRRn + 1 time intervals.
21.2.5
Each DTCRn latches the corresponding DTCNn value during a capture operation when an edge occurs on
DTINn, as programmed in DTMRn. The internal bus clock is assumed to be the clock source. DTINn
cannot simultaneously function as a clocking source and as an input capture pin. Indeterminate operation
results if DTINn is set as the clock source when the input capture mode is used.
Freescale Semiconductor
Field
Field
31–0
31–0
CAP
REF
IPSBAR
IPSBAR
Offset:
Offset:
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reference value compared with the respective free-running timer counter (DTCNn) as part of the output-compare
function.
Captures the corresponding DTCNn value during a capture operation when an edge occurs on DTIN
programmed in DTMRn.
W
W
R
R
DMA Timer Reference Registers (DTRRn)
DMA Timer Capture Registers (DTCRn)
0x00_0404 (DTRR0)
0x00_0444 (DTRR1)
0x00_0484 (DTRR2)
0x00_04C4 (DTRR3)
0x00_0408 (DTCR0)
0x00_0448 (DTCR1)
0x00_0488 (DTCR2)
0x00_04C8 (DTCR3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 21-5. DTRRn Field Descriptions
Table 21-6. DTCRn Field Descriptions
Figure 21-6. DTCRn Registers
Figure 21-5. DTRRn Registers
CAP (32-bit capture counter value)
REF (32-bit reference value)
Description
Description
8
8
7
7
Access: User read/write
Access: User read-only
6
6
DMA Timers (DTIM0–DTIM3)
5
5
4
4
3
3
n
2
2
, as
1
1
0
0
21-7