mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 760

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

Remote frames 25-11
Reset controller
Index-12
timers
UART modules
watchdog timer
block diagram 29-1
control flow 29-7
electrical characteristics
features 29-1
low-power modes 7-9
memory map 29-2
overview 29-1
registers
requests
sources of reset 29-5
DTIM
PIT
auxiliary control (UACRn) 23-13
baud rate generator (UBG1n/UBG2n) 23-15
clock select (UCSRn) 23-9
command (UCRn) 23-9
input port (UIPn) 23-15
input port change (UIPCRn) 23-12
interrupt status/mask (UISRn/UIMRn) 23-13
mode 1 (UMR1n) 23-5
mode 2 (UMRn) 23-6
output port command (UOP1n/UOP0n) 23-16
receive buffers (URBn) 23-11
status (USRn) 23-8
transmit buffers (UTBn) 23-12
control (WCR) 18-3
count (WCNTR) 18-5
modulus (WMR) 18-4
service (WSR) 18-5
reset and configuration override timing 33-19
control (RCR) 29-3
status (RSR) 29-4
internal 29-9
synchronous 29-9
external reset 29-6
LDV reset 29-6
loss-of-clock reset 29-6
loss-of-lock reset 29-6
initialization 15-23
settings 15-18
capture (DTCRn) 21-7
counters (DTCNn) 21-8
event (DTERn) 21-5
mode (DTMRn) 21-3
reference (DTRRn) 21-7
control and status (PCSR) 19-3
count (PCNTR) 19-5
modulus (PMR) 19-5
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Run mode 7-5
Rx/Tx frames 25-6
S
SACU
SAMPLE/PRELOAD instructions 31-7
Sampling mode (SAMP) 25-21
S-clock 25-12
SCM
SDRAM controller
status flags 29-10
timing diagrams
features 8-12
overview 8-11
features 8-1
low-power modes 7-7
memory map 8-2
overview 8-1
registers
SACU 8-11
auto-refresh 15-15
block diagram 15-1
burst page mode 15-13
definitions 15-1
example
initialization 15-17
interfacing 15-13
memory map 15-4
operation
power-on reset 29-6
software reset 29-6
watchdog timer reset 29-6
RSTI and configuration override 33-20
bus master park (MPARK) 8-9
core reset status (CRSR) 8-5
core watchdog control (CWCR) 8-5
core watchdog service (CWSR) 8-7
grouped peripheral access control (GPACRn) 8-15
IPSBAR 8-2
master privilege (MPR) 8-13
peripheral access control (PACRn) 8-13
RAMBAR 5-1
features 8-12
overview 8-11
DACR initialization 15-20
DCR initialization 15-20
DMR initialization 15-22
initialization code 15-23
interface configuration 15-20
general 15-3
low-power modes 7-7
synchronous
,
,
8-3
8-12
Freescale Semiconductor