mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 287

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

Accesses in synchronous burst page mode always cause the following sequence:
15.2.3.5 Auto-Refresh Operation
The DRAM controller is equipped with a refresh counter and control. This logic is responsible for
providing timing and control to refresh the SDRAM without user interaction. Once the refresh counter is
set, and refresh is enabled, the counter counts to zero. At this time, an internal refresh request flag is set
and the counter begins counting down again. The DRAM controller completes any active burst operation
and then performs a
refresh request flag. This refresh cycle includes a delay from any precharge to the auto-refresh command,
the auto-refresh command, and then a delay until any
initiated during the auto-refresh cycle is delayed until the cycle is completed.
Freescale Semiconductor
SDRAM_CS[0] or [1]
1.
2.
3. Required number of
4. Some transfers need more
5.
6. Required number of idle clocks inserted to assure precharge-to-
ACTV
NOP
commands).
size.
PALL
CLKOUT
DRAMW
commands to assure SRAS-to-SCAS delay (if CAS latency is 1, there are no
command
D[31:0]
BS[3:0]
command
A[23:0]
SRAS
SCAS
PALL
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
t
CASL
ACTV
operation. The DRAM controller then initiates a refresh cycle and clears the
READ
Row
= 2
Figure 15-7. Burst Write SDRAM Access
NOP
NOP
or
WRITE
Column
commands to assure the
WRITE
commands to service the transfer size with the given port
Column Column
WRITE
ACTV
WRITE
command is allowed. Any SDRAM access
t
RWL
ACTV
WRITE
-to-precharge delay.
ACTV
Column
NOP
Synchronous DRAM Controller Module
delay.
PALL
t
RP
NOP
15-15