mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 434

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

UART Modules
23-14
RXRDY
FFULL/
TXRDY
Field
COS
6–3
DB
7
2
1
0
(UIMRn)
IPSBAR
(UISRn)
Offset:
Reset:
Change-of-state.
0 UIPCRn[COS] is not selected.
1 Change-of-state occurred on UCTSn and was programmed in UACRn[IEC] to cause an interrupt.
Reserved, must be cleared.
Delta break.
0 No new break-change condition to report.
1 The receiver detected the beginning or end of a received break.
Status of FIFO or receiver, depending on UMR1[FFULL/RXRDY] bit. Duplicate of USRn[FIFO] and USRn[RXRDY]
Transmitter ready. This bit is the duplication of USRn[TXRDY].
0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters loaded into the
1 The transmitter holding register is empty and ready to be loaded with a character.
W
R
RESET BREAK
transmitter holding register when TXRDY is cleared are not sent.
0x00_0214 (UISR0)
0x00_0254 (UISR1)
0x00_0294 (UISR2)
True status is provided in the UISRn regardless of UIMRn settings. UISRn
is cleared when the UART module is reset.
COS
COS
0
7
Figure 23-12. UART Interrupt Status/Mask Registers (UISRn/UIMRn)
-
[FFULL/RXRDY]
CHANGE INTERRUPT
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
UIMRn
6
0
0
0
0
1
0
1
Table 23-10. UISRn/UIMRn Field Descriptions
[FFULL/RXRDY]
command.
0
0
0
5
UISRn
0
0
1
1
Section 23.3.5, “UART Command Registers
NOTE
0
0
0
4
Description
Receiver not ready
Receiver not ready
Receiver is ready,
Receiver is ready,
Do not interrupt
0 (RXRDY)
interrupt
0
0
0
3
UMR1n[FFULL/RXRDY]
DB
DB
0
2
Do not interrupt
FIFO not full
FIFO not full
FIFO is full,
FIFO is full,
1 (FIFO)
interrupt
Access: User read/write
FFULL/
RXRDY
FFULL/
RXRDY
(UCRn),” describes the
Freescale Semiconductor
0
1
TXRDY
TXRDY
0
0