mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 762

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

SRAM
Index-14
overview 14-1
power and reference
QADC
QSPI
reset controller
SDRAM controller
single-chip mode 14-17
TEST 14-31
UART modules
test data input/development serial input (TDI/DSI) 31-3
test data output/development serial output
test mode select/breakpoint (TMS/BKPT) 31-3
test reset/development serial clock
V
V
V
V
V
V
V
V
V
analog input (ANn/ANx) 14-28
analog power (V
analog reference (V
dedicated digital I/O port supply (V
external trigger input (ETRIG2–1) 28-5
multiplexed address output (MA1–0) 28-5
multiplexed analog input (ANx) 28-5
port QA analog input (AN56–55, 53–52) 28-4
port QA digital input/output (PQA4–3, 1–0) 28-4
port QB analog input (AN3–0) 28-4
port QB digital I/O (PQB3–0) 28-5
chip select (QSPI_CS3–0) 14-25
serial clock (QSPI_CLK) 14-25
summary 22-2
synchronous serial data input (QSPI_DIN) 14-25
synchronous serial data output (QSPI_DOUT) 14-25
reset in (RSTI) 14-22
reset out (RSTO) 29-2
bank select (SDRAM_CS1–0) 14-21
clock enable (SCKE) 14-22
column address strobe (SCAS) 14-21
row address strobe (SRAS) 14-21
summary 15-4
write enable (DRAMW) 14-21
clear-to-send (UCTS1–0) 14-26
receive serial data input (URXD2–0) 14-26
request-to-send (URTS1–0) 14-27
transmit serial data output (UTXD2–0) 14-26
DD
DDA
DDF
DDH
DDPLL
PP
RH
SS
STBY
(TDO/DSO) 31-4
(TRST/DSCLK) 31-3
,
14-32
14-32
, V
14-32
VRL
, V
14-32
14-32
, V
SSF
SSA
14-32
SSPLL
14-32
14-32
DDA
14-32
RH
, V
,
, V
29-2
SSA)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
RL
) 28-56
28-56
–
14-29
DDH
) 28-6
Stack pointer 2-5
Stack pointer registers
Start-of-frame (SOF) 25-13
STOP instruction 30-4
Stop mode 7-6
STUFFERR 25-26
System clock
T
TAP controller 31-6
TEST_LEAKAGE 31-8
Time quanta clock 25-12
Time stamp 25-6
Timer overflow interrupt 20-22
Timers
cache, interaction 4-7
features 5-1
initialization 5-3
operation
overview 5-1
power management 5-4
programming model 5-1
timing diagrams
BDM accesses 30-33
generation 9-11
modes 9-10
DTIM
general purpose, see general purpose timers
PIT
low-power modes 7-6
bus cycle terminated by TA 33-15
bus cycle terminated by TEA 33-16
capture mode 21-8
code example 21-9
operation
output mode 21-9
prescaler 21-8
reference compare 21-8
registers
time-out values 21-10
block diagram 19-1
interrupts 19-7
memory map 19-2
operation
general 21-9
capture (DTCRn) 21-7
counters (DTCNn) 21-8
event (DTERn) 21-5
mode (DTMRn) 21-3
reference (DTRRn) 21-7
free-running 19-6
low-power modes 19-1
,
25-12
,
30-17
Freescale Semiconductor