mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 319

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

17.4.2
When an event occurs that sets a bit in EIR, an interrupt occurs if the corresponding bit in the interrupt
mask register (EIMR) is also set. Writing a 1 to an EIR bit clears it; writing 0 has no effect. This register
is cleared upon hardware reset.
These interrupts can be divided into operational interrupts, transceiver/network error interrupts, and
internal error interrupts. Interrupts which may occur in normal operation are GRA, TXF, TXB, RXF, RXB,
and MII. Interrupts resulting from errors/problems detected in the network or transceiver are HBERR,
BABR, BABT, LC, and RL. Interrupts resulting from internal errors are HBERR and UN.
Some of the error interrupts are independently counted in the MIB block counters:
Software may choose to mask off these interrupts because these errors are visible to network management
via the MIB counters.
Freescale Semiconductor
IPSBAR
Offset:
Reset
Reset
•
•
•
•
•
•
W w1c
W
R
R
HBERR - IEEE_T_SQE
BABR - RMON_R_OVERSIZE (good CRC), RMON_R_JAB (bad CRC)
BABT - RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC)
LATE_COL - IEEE_T_LCOL
COL_RETRY_LIM - IEEE_T_EXCOL
XFIFO_UN - IEEE_T_MACERR
0x1004
IPSBAR Offset
ERR
HB
31
15
0
0
0
0x12DC
Ethernet Interrupt Event Register (EIR)
0x12E0
BABR BABT GRA
w1c
30
14
0
0
0
w1c
29
13
0
0
0
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Flow control pause frames received (IEEE_R_FDXFC)
Octet count for frames received without error (IEEE_R_OCTETS_OK)
Figure 17-2. Ethernet Interrupt Event Register (EIR)
Table 17-4. MIB Counters Memory Map (continued)
w1c
28
12
0
0
0
TXF
w1c
27
11
0
0
0
TXB
w1c
26
10
0
0
0
RXF
w1c
25
0
0
0
9
RXB
w1c
24
0
0
0
8
Register
w1c
MII
23
0
0
0
7
ERR
w1c
EB
22
0
0
0
6
w1c
LC
21
0
0
0
5
w1c
RL
20
0
0
0
4
Fast Ethernet Controller (FEC)
w1c
UN
19
0
0
0
3
Access: User read/write
18
0
0
2
0
0
17
0
0
0
0
1
16
17-9
0
0
0
0
0