mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 536

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

Chip Configuration Module (CCM)
27.6.2
The chip mode is selected during reset and reflected in the MODE field of the chip configuration register
(CCR). See
mode cannot be changed.
27-8
1
2
3
4
5
Modifying the default configurations is possible only if the external RCON pin is asserted.
The D[31:27, 23:22, 20, 15:0] pins do not affect reset configuration.
The external reset override circuitry drives the data bus pins with the override values while RSTO is asserted. It must stop
driving the data bus pins within one CLKOUT cycle after RSTO is negated. To prevent contention with the external reset
override circuitry, the reset override pins are forced to inputs during reset and do not become outputs until at least one
CLKOUT cycle after RSTO is negated.
RCON[0] has higher priority than RCON[3:2]. When RCON[0] is configured to boot the chip in single chip mode, the part will
boot internally with a 32-bit port overriding any configuration set by RCON[3:2].
Default configuration
A[23:21]/CS[6:4]
Pin(s) Affected
All output pins
Clock mode
Chip Mode Selection
CS0
Section 27.5.3.1, “Chip Configuration Register
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 27-9
Table 27-8. Configuration During Reset
RCON[4:3] = 00
RCON[9:8] = 00
Configuration
RCON2 = 0
RCON5 = 1
Default
N/A
shows the mode selection during reset configuration.
CLKMOD1, CLKMOD0
Override Pins
in Reset
D[19:18]
D[25:24]
D21
00
10
01
11
00
01
10
11
00
10
01
11
0
1
2,34
(CCR).” Once reset is exited, the operating
1
(continued)
Normal PLL mode w/crystal reference
External clock mode (PLL disabled)
PF[7:6] = CS6, CS5 / PF[5] = A[21]
PF[7] = CS6 / PF[6:5] = A[22:21]
Normal PLL mode with external
Output Pad Drive Strength
Chip Select Configuration
PF[7:6] = CS6, CS5, CS4
Internal with 32-bit port
External with 16-bit port
External with 32-bit port
External with 8-bit port
PF[7:5] = A[23:21]
Partial strength
clock reference
1:1 PLL mode
Full strength
Boot Device
Clock Mode
Function
Freescale Semiconductor
5
5
5