mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 192

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

Interrupt Controller Modules
Section 2.3.3.1, “Exception Stack Frame
After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer from the
exception vector table using the vector number as the offset, and then jumps to that address to begin
execution of the service routine. After the status register is stored in the exception stack frame, the SR[I]
mask field is set to the level of the interrupt being acknowledged, effectively masking that level and all
lower values while in the service routine. For many peripheral devices, the processing of the IACK cycle
directly negates the interrupt request, while other devices require that request to be explicitly negated
during the processing of the service routine.
For this device, the processing of the interrupt acknowledge cycle is fundamentally different than previous
68K/ColdFire cores. In the new approach, all IACK cycles are directly handled by the interrupt controller,
so the requesting peripheral device is not accessed during the IACK. As a result, the interrupt request must
be explicitly cleared in the peripheral during the interrupt service routine. For more information, see
Section 10.1.1.3, “Interrupt Vector
Unlike the M68000 family, all ColdFire processors guarantee that the first instruction of the service routine
is executed before sampling for interrupts is resumed. By making this initial instruction a load of the SR,
interrupts can be safely disabled, if required.
During the execution of the service routine, the appropriate actions must be performed on the peripheral
to negate the interrupt request.
For more information on exception processing, see the ColdFire Programmer’s Reference Manual at
http://www.freescale.com/coldfire.
10.1.1
To support the interrupt architecture of the 68K/ColdFire programming model, the combined 63 interrupt
sources are organized as 7 levels, with each level supporting up to 9 prioritized requests. Consider the
interrupt priority structure shown in
to lowest.
10-2
Interrupt Controller Theory of Operation
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Interrupt
ICR[IL]
Level
Table 10-1. Interrupt Priority Scheme
7
Determination.”
Table
Definition” for more information on the stack frame format).
10-1, which orders the interrupt levels/priorities from highest
— (Mid-point)
Priority
ICR[IP]
7
6
5
4
3
2
1
0
Supported Interrupt
#7 (IRQ7)
Sources
#8–63
#8–63
Freescale Semiconductor