mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 315

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

17.3
Table 17-1
17.4
The FEC is programmed by a combination of control/status registers (CSRs) and buffer descriptors. The
CSRs control operation modes and extract global status information. The descriptors pass data buffers and
related buffer information between the hardware and software.
Each FEC implementation requires a 1-Kbyte memory map space, which is divided into two sections of
512 bytes each for:
Freescale Semiconductor
FEC_RXD[3:2]
FEC_TXD[3:2]
Signal Name
FEC_RXCLK
FEC_TXCLK
FEC_RXER
FEC_MDIO
FEC_RXDV
FEC_RXD0
FEC_RXD1
FEC_TXEN
FEC_TXER
FEC_TXD0
FEC_TXD1
FEC_MDC
FEC_CRS
FEC_COL
External Signal Description
Memory Map/Register Definition
describes the various FEC signals, as well as indicating which signals work in available modes.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
— When asserted, indicates that transmit or receive medium is not idle.
— Output clock which provides a timing reference to the PHY for data transfers on the FEC_MDIO
— Transfers control information between the external PHY and the media-access controller. Data
— This pin contains the Ethernet input data transferred from the PHY to the media access
— These pins contain the Ethernet input data transferred from the PHY to the media access
— When asserted with FEC_RXDV, indicates that the PHY has detected an error in the current
— This pin contains the serial output Ethernet data and is valid only during assertion of
— These pins contain the serial output Ethernet data and are valid only during assertion of
— When asserted for one or more clock cycles while FEC_TXEN is also asserted, the PHY sends
X
X
X
X
X
X
X
Asserted upon detection of a collision and remains asserted while the collision persists. This
signal is not defined for full-duplex mode.
signal.
is synchronous to FEC_MDC. This signal is an input after reset. When the FEC is operated in
10Mbps 7-wire interface mode, this signal should be connected to VSS.
Provides a timing reference for FEC_RXDV, FEC_RXD[3:0], and FEC_RXER.
Asserting the FEC_RXDV input indicates that the PHY has valid nibbles present on the MII.
FEC_RXDV should remain asserted from the first recovered nibble of the frame through to the
last nibble. Assertion of FEC_RXDV must start no later than the SFD and exclude any EOF.
This pin contains the Ethernet input data transferred from the PHY to the media-access
controller when FEC_RXDV is asserted.
controller when FEC_RXDV is asserted.
controller when FEC_RXDV is asserted.
frame. When FEC_RXDV is not asserted FEC_RXER has no effect.
Input clock which provides a timing reference for FEC_TXEN, FEC_TXD[3:0] and FEC_TXER.
The serial output Ethernet data and is only valid during the assertion of FEC_TXEN.
FEC_TXEN.
FEC_TXEN.
Indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble
of a preamble and is negated before the first FEC_TXCLK following the final nibble of the frame.
one or more illegal symbols. FEC_TXER has no effect at 10 Mbps or when FEC_TXEN is
negated.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 17-1. FEC Signal Descriptions
Description
Fast Ethernet Controller (FEC)
17-5