mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 327

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

17.4.11 Transmit Control Register (TCR)
TCR is read/write and configures the transmit block. This register is cleared at system reset. Bits 2 and 1
must be modified only when ECR[ETHER_EN] is cleared.
Freescale Semiconductor
IPSBAR
MII_MODE
Offset:
MAX_FL
BC_REJ
Reset
Reset
PROM
31–27
26–16
LOOP
Field
15–6
FCE
DRT
5
4
3
2
1
0
W
W
R
R
0x1084
31
15
0
0
0
0
Reserved, must be cleared.
Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the
end of the frame. Transmit frames longer than MAX_FL causes the BABT interrupt to occur. Receive frames longer
than MAX_FL causes the BABR interrupt to occur and sets the LG bit in the end of frame receive buffer descriptor.
The recommended default value to be programmed is 1518 or 1522 if VLAN tags are supported.
Reserved, must be cleared.
Flow control enable. If asserted, the receiver detects PAUSE frames. Upon PAUSE frame detection, the transmitter
stops transmitting data frames for a given duration.
Broadcast frame reject. If asserted, frames with DA (destination address) equal to FFFF_FFFF_FFFF are rejected
unless the PROM bit is set. If BC_REJ and PROM are set, frames with broadcast DA are accepted and the M
(MISS) is set in the receive buffer descriptor.
Promiscuous mode. All frames are accepted regardless of address matching.
Media independent interface mode. Selects the external interface mode for transmit and receive blocks.
0 7-wire mode (used only for serial 10 Mbps)
1 MII mode
Disable receive on transmit.
0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex
1 Disable reception of frames while transmitting (normally used for half duplex mode).
Internal loopback. If set, transmitted frames are looped back internal to the device and transmit output signals are
not asserted. The internal bus clock substitutes for the FEC_TXCLK when LOOP is asserted. DRT must be set to
0 when setting LOOP.
mode).
30
14
0
0
0
0
29
13
0
0
0
0
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
28
12
0
0
0
0
Figure 17-10. Receive Control Register (RCR)
27
11
0
0
0
0
Table 17-14. RCR Field Descriptions
26
10
1
0
0
25
0
0
0
9
24
1
8
0
0
Description
23
1
0
0
7
22
1
0
0
6
MAX_FL
FCE
21
1
5
0
BC_
REJ
20
0
4
0
Fast Ethernet Controller (FEC)
PROM
19
1
0
3
Access: User read/write
MODE
MII_
18
1
0
2
DRT LOOP
17
1
0
1
17-17
16
0
0
1