mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 620

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

Debug Support
30.2
Table 30-1
rising edge of the processor’s clock signal. The standard 26-pin debug connector is shown in
“Freescale-Recommended BDM
Figure 30-2
30.3
Real-time trace, which defines the dynamic execution path, is a fundamental debug function. The ColdFire
solution is to include a parallel output port providing encoded processor status and data to an external
development system. This port is partitioned into two 4-bit nibbles: one nibble allows the processor to
transmit processor status, (PST), and the other allows operand data to be displayed (debug data, DDATA).
The processor status may not be related to the current bus transfer.
External development systems can use PST outputs with an external image of the program to completely
track the dynamic execution path. This tracking is complicated by any change in flow, especially when
30-2
Development Serial
Clock (DSCLK)
Development Serial
Input (DSI)
Development Serial
Output (DSO)
Breakpoint (BKPT)
CLKOUT
Debug Data
(DDATA[3:0])
Processor Status
(PST[3:0])
Signal
Signal Description
Real-Time Trace Support
describes debug module signals. All ColdFire debug signals are unidirectional and related to a
shows CLKOUT timing with respect to PST and DDATA.
PST
CLKOUT
or
DDATA
Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on
two consecutive rising CLKOUT edges.) Clocks the serial communication port to the debug
module during packet transfers. Maximum frequency is 1/5 the processor status clock (CLKOUT)
speed. At the synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO
changes state.
Internally synchronized input that provides data input for the serial communication port to the
debug module.
Provides serial output communication for debug module responses. DSO is registered internally.
Input used to request a manual breakpoint. Assertion of BKPT puts the processor into a halted
state after the current instruction completes. Halt status is reflected on processor status signals
(PST[3:0]) as the value 0xF.
See
DDATA values.
These output signals display the register breakpoint status as a default, or optionally, captured
address and operand values. The capturing of data values is controlled by the setting of the CSR.
Additionally, execution of the WDDATA instruction by the processor captures operands which are
displayed on DDATA. These signals are updated each processor cycle.
These output signals report the processor status.
signals. These outputs indicate the current status of the processor pipeline and, as a result, are
not related to the current bus transfer. The PST value is updated each processor cycle.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure
30-2. CLKOUT indicates when the development system should sample PST and
Pinout.”
Table 30-1. Debug Module Signals
Figure 30-2. CLKOUT Timing
Description
Table 30-2
shows the encoding of these
Freescale Semiconductor
Section 30.8,