mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 631

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

Table 30-9
Table 30-10
The DBR supports both aligned and misaligned references.
processor address, access size, and location within the 32-bit data bus.
30.4.6
The PBR defines an instruction address for use as part of the trigger. This register’s contents are compared
with the processor’s program counter register when TDR is configured appropriately. PBR bits are masked
by setting corresponding PBMR bits. Results are compared with the processor’s program counter register,
as defined in TDR.
Freescale Semiconductor
31–0
31–0
Bits
Bits
describes DBR fields.
Name
Program Counter Breakpoint/Mask Registers (PBR, PBMR)
Name
Mask
Data
describes DBMR fields.
Data breakpoint value. Contains the value to be compared with the data value from the processor’s
local bus as a breakpoint trigger.
Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBR bit allows the
corresponding DBR bit to be compared to the appropriate bit of the processor’s local data bus. Setting
a DBMR bit causes that bit to be ignored.
Figure 30-9
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 30-11. Access Size and Operand Data Location
shows the PC breakpoint register.
A[1:0]
00
01
10
11
Table 30-10. DBMR Field Descriptions
0x
1x
xx
Table 30-9. DBR Field Descriptions
Access Size
Longword
Word
Word
Byte
Byte
Byte
Byte
Description
Description
Operand Location
Table 30-11
D[31:24]
D[23:16]
D[31:16]
D[15:8]
D[15:0]
D[31:0]
D[7:0]
shows relationships between
Debug Support
30-13