mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 628

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

Debug Support
Table 30-6
Table 30-7
30.4.4
The CSR defines the debug configuration for the processor and memory subsystem and contains status
information from the breakpoint logic. CSR is write-only from the programming model. It can be read
from and written to through the BDM port. CSR is accessible in supervisor mode as debug control register
0x00 using the WDEBUG instruction and through the BDM port using the
commands.
30-10
DRc[4–0]
31–0 Address High address. Holds the 32-bit address marking the upper bound of the address breakpoint range.
Bits
31–0
Bits
Reset
Reset
R/W
Field
Field MAP TRC EMU
R/W R/W R/W R/W
1
describes ABLR fields.
Address Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range.
describes ABHR fields.
Configuration/Status Register (CSR)
Name
Name
31
15
Breakpoints for specific addresses are programmed into ABLR.
14
BSTAT
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
13
Figure 30-7. Configuration/Status Register (CSR)
28
12
DDC
R/W
Table 30-7. ABHR Field Description
Table 30-6. ABLR Field Description
FOF TRG HALT BKPT
27
11
UHE
R/W
26
10
R
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
25
9
BTB
R/W
24
8
Description
Description
—
23
R
7
NPL
R/W R/W R/W
6
HRL
IPI
5
SSM
20
4
RDMREG
19
3
Freescale Semiconductor
—
—
—
—
and
17
WDMREG
IPW
R/W
16
0