mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 545

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

28.6
This subsection describes the QADC registers.
28.6.1
The QADCMCR contains bits that control QADC debug and stop modes and determine the privilege level
required to access most registers.
Freescale Semiconductor
1
2
3
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to
supervisor only addresses have no effect and result in a cycle termination transfer error.
Access results in the module generating an access termination transfer error if not in test mode.
Read/writes have no effect and the access terminates with a transfer error exception.
Address
0x19_0014–
0x19_0200–
0x19_0280–
0x19_0300–
0x19_0380–
0x19_027e
0x19_037e
IPSBAR +
0x19_01fe
0x19_02fe
0x19_03fe
Reset
Reset
R/W:
Field
R/W:
Field
Offset
Register Descriptions
QADC Module Configuration Register (QADCMCR)
QSTOP
SUPV
R/W
15
7
Figure 28-3. QADC Module Configuration Register (QADCMCR)
R/W
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
QDBG
14
6
Table 28-2. QADC Memory Map (continued)
Right Justified, Unsigned Result Register (RJURR)
Left Justified, Unsigned Result Register (LJURR)
Left Justified, Signed Result Register (LJSRR)
MSB
Conversion Command Word Table (CCW)
13
IPSBAR + 0x19_0000, 0x19_0001
Reserved
0000_0000
1000_0000
(3)
—
R
—
R
Queued Analog-to-Digital Converter (QADC)
LSB
Access
8
0
S/U
S/U
S/U
S/U
—
1
28-7