mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 206

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

Interrupt Controller Modules
10.3.7
The eight IACK registers can be explicitly addressed via the CPU, or implicitly addressed via a
processor-generated interrupt acknowledge cycle during exception processing. In either case, the interrupt
controller’s actions are very similar.
First, consider an IACK cycle to a specific level: that is, a level-n IACK. When this type of IACK arrives
in the interrupt controller, the controller examines all the currently-active level n interrupt requests,
determines the highest priority within the level, and then responds with the unique vector number
corresponding to that specific interrupt source. The vector number is supplied as the data for the byte-sized
IACK read cycle. In addition to providing the vector number, the interrupt controller also loads the level
and priority number for the level into the IACKLPR register, where it may be retrieved later.
This interrupt controller design also supports the concept of a software IACK. A software IACK is a useful
concept that allows an interrupt service routine to determine if there are other pending interrupts so that
the overhead associated with interrupt exception processing (including machine state save/restore
functions) can be minimized. In general, the software IACK is performed near the end of an interrupt
10-16
Source Module
27-63
1-7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
8
9
Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)
FLEX
CAN
WAKE_INT Wake-up interrupt
BOFF_INT Bus-off interrupt
ERR_INT
BUF10I
BUF11I
BUF12I
BUF13I
BUF14I
BUF15I
BUF0I
BUF1I
BUF2I
BUF3I
BUF4I
BUF5I
BUF6I
BUF7I
BUF8I
BUF9I
Flag
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 10-14. Interrupt Source Assignment for INTC1
Message buffer 0 interrupt
Message buffer 1 interrupt
Message buffer 2 interrupt
Message buffer 3 interrupt
Message buffer 4 interrupt
Message buffer 5 interrupt
Message buffer 6 interrupt
Message buffer 7 interrupt
Message buffer 8 interrupt
Message buffer 9 interrupt
Message buffer 10 interrupt
Message buffer 11 interrupt
Message buffer 12 interrupt
Message buffer 13 interrupt
Message buffer 14 interrupt
Message buffer 15 interrupt
Error interrupt
Source Description
Not Used
Not used
Write BUF0I = 1 after reading BUF0I = 1
Write BUF1I = 1 after reading BUF1I = 1
Write BUF2I = 1 after reading BUF2I = 1
Write BUF3I = 1 after reading BUF3I = 1
Write BUF4I = 1 after reading BUF4I = 1
Write BUF5I = 1 after reading BUF5I = 1
Write BUF6I = 1 after reading BUF6I = 1
Write BUF7I = 1 after reading BUF7I = 1
Write BUF8I = 1 after reading BUF8I = 1
Write BUF9I = 1 after reading BUF9I = 1
Write BUF10I = 1 after reading BUF10I = 1
Write BUF11I = 1 after reading BUF11I = 1
Write BUF12I = 1 after reading BUF12I = 1
Write BUF13I = 1 after reading BUF13I = 1
Write BUF14I = 1 after reading BUF14I = 1
Write BUF15I = 1 after reading BUF15I = 1
Write ERR_INT = 1 after reading ERR_INT = 1
Write BOFF_INT = 1 after reading BOFF_INT = 1
Write WAKE_INT = 1 after reading WAKE_INT = 1
Flag Clearing Mechanism
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