mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 499

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

Table 25-19
25.5.11 FlexCAN Receive Error Counter (RXECTR)
Table 25-20
Freescale Semiconductor
Bits
15–0
7–0
Bits
Address
Address
Reset
Reset
Reset
Field
Field
Field
R/W
R/W
R/W
RXECT
BUFnI IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception sets the
Name
Name
describes the IFLAG fields.
describes the RXECTR fields.
R
BUF15I
BUF7I
corresponding IFLAG bit and, if the corresponding IMASK bit is set, an interrupt request will be
generated.
To clear an interrupt flag, first read the flag as a one, and then write it as a one. Should a new flag
setting event occur between the time that the CPU reads the flag as a one and writes the flag as a
zero, the flag is not cleared. This register can be written to zeros only.
0 The interrupt for the corresponding buffer is disabled.
1 The interrupt for the corresponding buffer is enabled.
Receive error counter. Indicates the current receive error count as defined in the CAN protocol. See
Section 25.4.9, “FlexCAN Error
15
7
7
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 25-16. FlexCAN Receive Error Counter (RXECTR)
BUF14I
BUF6I
14
6
Figure 25-15. Interrupt Flag Register (IFLAG)
Table 25-20. RXECTR Field Descriptions
Table 25-19. IFLAG Field Descriptions
BUF13I
BUF5I
13
5
Counters” for more details.
IPSBAR + 0x1C_0024
IPSBAR + 0x1C_0026
BUF1I
BUF4I
12
4
0000_0000
0000_0000
0000_0000
RXECTR
Description
Description
R/W
R/w
R
BUF11I
BUF3I
11
3
BUF10I
BUF2I
10
BUF9I
BUF1I
9
BUF8I
BUF0I
8
0
0
FlexCAN
25-29