mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 329

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

17.4.13 Physical Address Upper Register (PAUR)
PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in the address recognition
process to compare with the DA (destination address) field of receive frames with an individual DA. In
addition, this register is used in bytes 4 and 5 of the 6-byte Source Address field when transmitting PAUSE
frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for transmission of PAUSE frames. The
upper 16 bits of this register are not reset and you must initialize it.
17.4.14 Opcode/Pause Duration Register (OPD)
The OPD is read/write accessible. This register contains the 16-bit opcode and 16-bit pause duration fields
used in transmission of a PAUSE frame. The opcode field is a constant value, 0x0001. When another node
detects a PAUSE frame, that node pauses transmission for the duration specified in the pause duration
field. The lower 16 bits of this register are not reset and you must initialize them.
Freescale Semiconductor
PADDR1
PADDR2
31–16
TYPE
Field
Field
31–0
15–0
IPSBAR
IPSBAR
Offset:
Offset:
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Reset — — — — — — — — — — — — — — — — 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used for exact
match and the source address field in PAUSE frames.
Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address
field in PAUSE frames.
Type field in PAUSE frames. These 16 read-only bits are a constant value of 0x8808.
W
W
R
R
0x10E4
0x10E8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 17-12. Physical Address Lower Register (PALR)
Figure 17-13. Physical Address Upper Register (PAUR)
PADDR2
Table 17-16. PALR Field Descriptions
Table 17-17. PAUR Field Descriptions
Description
Description
PADDR1
TYPE
8
8
7
7
Access: User read/write
Access: User read/write
Fast Ethernet Controller (FEC)
6
6
5
5
4
4
3
3
2
2
1
1
0
0
17-19