mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 294

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

Synchronous DRAM Controller Module
15.3.4
Again, in this example only the second 512-Kbyte block of each 1-Mbyte space is accessed in each bank.
In addition, the SDRAM component is mapped only to readable and writable supervisor and user data. The
DMRs have the following configuration.
With this configuration, the DMR0 = 0x0074_0075, as described in
15-22
31–18
17–16
15–9
Bits
Setting
Setting
8
7
6
5
4
3
2
1
0
(hex)
(hex)
Field
Field
DMR Initialization
Name
BAM
WP
AM
SC
SD
UC
UD
C/I
—
—
—
V
Bits
31
15
2–0
3
Setting
0
1
1
1
0
1
0
1
Name
IP
—
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
With bits 17 and 16 as don’t cares, BAM = 0x0074, which leaves bank select bits and upper
512K select bits unmasked. Note that bits 22 and 21 are set because they are used as bank
selects; bit 20 is set because it controls the 1-Mbyte boundary address.
Reserved. Don’t care.
Reserved. Don’t care.
Allow reads and writes
Reserved. Don’t care.
Disable CPU space access.
Disable alternate master access.
Disable supervisor code accesses.
Enable supervisor data accesses.
Disable user code accesses.
Enable user data accesses.
Enable accesses.
Table 15-28. DACR Initialization Values (continued)
—
Setting
Table 15-29. DMR0 Initialization Values
0
Figure 15-14. DMR0 Register
Indicates precharge has not been initiated.
Reserved. Don’t care.
0000_0000_0111_01xx
xxxx_xxx0_x111_0101
9
BAM
WP
8
0 074
0075
—
Description
7
Description
C/I
6
Table
AM
5
15-29.
SC
4
SD
3
Freescale Semiconductor
UC
18
2
UD
17
1
—
16
V
0