mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 320

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

Fast Ethernet Controller (FEC)
17.4.3
The EIMR register controls which interrupt events are allowed to generate actual interrupts. All
implemented bits in this CSR are read/write. A hardware reset clears this register. If the corresponding bits
in the EIR and EIMR registers are set, an interrupt is generated. The interrupt signal remains asserted until
a 1 is written to the EIR bit (write 1 to clear) or a 0 is written to the EIMR bit.
17-10
HBERR
EBERR
BABR
BABT
Field
18–0
GRA
RXB
TXB
RXF
TXF
MII
UN
LC
RL
31
30
29
28
27
26
25
24
23
22
21
20
19
Transmit FIFO underrun. Indicates the transmit FIFO became empty before the complete frame was transmitted. A
bad CRC is appended to the frame fragment and the remainder of the frame is discarded.
Reserved, must be cleared.
Heartbeat error. Indicates TCR[HBC] is set and that the COL input was not asserted within the heartbeat window
following a transmission.
Babbling receive error. Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
Babbling transmit error. Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually this condition
is caused by a frame that is too long is placed into the transmit data buffer(s). Truncation does not occur.
Graceful stop complete. Indicates the graceful stop is complete. During graceful stop the transmitter is placed into a
pause state after completion of the frame currently being transmitted. This bit is set by one of three conditions:
Transmit frame interrupt. Indicates a frame has been transmitted and the last corresponding buffer descriptor has
been updated.
Transmit buffer interrupt. Indicates a transmit buffer descriptor has been updated.
Receive frame interrupt. Indicates a frame has been received and the last corresponding buffer descriptor has been
updated.
Receive buffer interrupt. Indicates a receive buffer descriptor not the last in the frame has been updated.
MII interrupt. Indicates the MII has completed the data transfer requested.
Ethernet bus error. Indicates a system bus error occurred when a DMA transaction is underway. When the EBERR
bit is set, ECR[ETHER_EN] is cleared, halting frame processing by the FEC. When this occurs, software needs to
ensure that the FIFO controller and DMA also soft reset.
Late collision. Indicates a collision occurred beyond the collision window (slot time) in half duplex mode. The frame
truncates with a bad CRC and the remainder of the frame is discarded.
Collision retry limit. Indicates a collision occurred on each of 16 successive attempts to transmit the frame. The frame
is discarded without being transmitted and transmission of the next frame commences. This error can only occur in
half duplex mode.
1) A graceful stop initiated by the setting of the TCR[GTS] bit is now complete.
2) A graceful stop initiated by the setting of the TCR[TFC_PAUSE] bit is now complete.
3) A graceful stop initiated by the reception of a valid full duplex flow control pause frame is now complete. Refer
to
Interrupt Mask Register (EIMR)
Section 17.5.11, “Full Duplex Flow Control.”
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 17-5. EIR Field Descriptions
Description
Freescale Semiconductor