mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 304

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

DMA Controller Module
Table 16-3
16-8
1
Address
Available only if BCR24BIT = 1, otherwise reserved.
Bits
Reset
Reset
31
30
29
28
Field INT EEXT
Field AT
R/W
R/W
describes DCRn fields.
Name
EEXT
31
15
INT
0
CS
AA
1
30
14
Interrupt on completion of transfer. Determines whether an interrupt is generated by completing a
transfer or by the occurrence of an error condition.
0 No interrupt is generated.
1 Internal interrupt signal is enabled.
Enable external request. Care should be taken because a collision can occur between the START bit
and DREQ when EEXT = 1.
0 External request is ignored.
1 Enables external request to initiate transfer. The internal request (initiated by setting the START
Cycle steal.
0 DMA continuously makes read/write transfers until the BCR decrements to 0.
1 Forces a single read/write transfer per request. The request may be internal by setting the START
Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that is,
transfers are optimized based on the address and size. See
0 Auto-align disabled
1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise,
bit) is always enabled.
bit, or external by asserting DREQ.
destination accesses are auto-aligned. Source alignment takes precedence over destination
alignment. If auto-alignment is enabled, the appropriate address register increments, regardless
of DINC or SINC.
CS
29
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
AA
28
Figure 16-8. DMA Control Registers (DCRn)
Table 16-3. DCRn Field Descriptions
27
BWC
IPSBAR + 0x108, 0x148, 0x188, 0x1C8
25
0000_0000_0000_0000
24
—
R/W
R/W
Description
23
—
N/A
—
SINC
22
Section 16.5.4.1,
21
SSIZE
20
DINC
19
“Auto-Alignment.”
Freescale Semiconductor
18
DSIZE
17
START
16
0