mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 705

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

Figure 33-10
33.13 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
33.13.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK)
The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
ERXCLK frequency.
Table 33-21
Freescale Semiconductor
SDA
SCL
1
2
3
Table 33-20. I
lists MII receive channel timings.
shows timing for the values in
Num
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed
with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in
Table
the middle of the SCL low period. The actual position is affected by the prescale and division
values programmed into the IFDR; however, the numbers given in
values.
Because SCL and SDA are open-collector-type outputs, which the processor can only actively
drive low, the time SCL or SDA take to reach a high level depends on external signal capacitance
and pull-up resistor values.
Specified at a nominal 50-pF load.
I8
I9
The MCF5214 and MCF5216 do not contain an FEC module.
1
1
I1
33-20. The I
Start condition setup time (for repeated start
condition only)
Stop condition setup time
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
2
C Output Timing Specifications between SCL and SDA (continued)
I2
2
C interface is designed to scale the actual data transition time to move it to
I4
Figure 33-10. I
Characteristic
Table 33-19
I6
2
C Input/Output Timings
NOTE
I7
and
Table
Min
20
10
I8
33-20.
Table 33-20
Max
—
—
I5
I3
are minimum
Bus clocks
Bus clocks
Units
Electrical Characteristics
I9
33-21