mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 172

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

Clock Module
9.3
This subsection describes the operation of the clock module in low-power and halted modes of operation.
Low-power modes are described in
operation in low-power modes.
During wakeup from a low-power mode, the Flash clock always clocks through at least 16 cycles before
the CPU clocks are enabled. This allows the Flash module time to recover from the low-power mode, and
software can immediately resume fetching instructions from memory.
In wait and doze modes, the system clocks to the peripherals are enabled, and the clocks to the CPU, Flash,
and SRAM are stopped. Each module can disable its clock locally at the module level.
In stop mode, all system clocks are disabled. There are several options for enabling or disabling the PLL
or crystal oscillator in stop mode, compromising between stop mode current and wakeup recovery time.
The PLL can be disabled in stop mode, but requires a wakeup period before it can relock. The oscillator
can also be disabled during stop mode, but requires a wakeup period to restart.
When the PLL is enabled in stop mode (STPMD[1:0]), the external CLKOUT signal can support systems
using CLKOUT as the clock source.
There is also a fast wakeup option for quickly enabling the system clocks during stop recovery. This
eliminates the wakeup recovery time but at the risk of sending a potentially unstable clock to the system.
To prevent a non-locked PLL frequency overshoot when using the fast wakeup option, change the RFD
divisor to the current RFD value plus one before entering stop mode.
In external clock mode, there are no wakeup periods for oscillator startup or PLL lock.
9.4
Figure
detail in
9-2
Low-power Mode
shows a block diagram of the entire clock module. The PLL block in this diagram is expanded in
Figure
Low-power Mode Operation
Block Diagram
Halted
Doze
Stop
Wait
9-2.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 9-1. Clock Module Operation in Low-power Modes
Clocks sent to peripheral modules only
Clocks sent to peripheral modules only
All system clocks disabled
Clock Operation
Chapter 7, “Power
Normal
Management.”
Exit not caused by clock module, but normal
Exit not caused by clock module, but normal
sources are re-enabled and normal clocking
Exit not caused by clock module, but clock
clocking resumes upon mode exit
clocking resumes upon mode exit
Exit not caused by clock module
Table 9-1
resumes upon mode exit
Mode Exit
shows the clock module
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