AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 114

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 41. TAP 8-bit DR Register
Device Operations
Flash Read Command
114
AT91SAM7S32 Preliminary
TDI
r/w
Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data
field, a 5-bit address field and a read/write bit. The data to be written is scanned into the 32-bit
data field with the address of the register to the 5-bit address field and 1 to the read/write bit. A
register is read by scanning its address into the address field and 0 into the read/write bit,
going through the UPDATE-DR TAP state, then scanning out the data. The 32-bit data field is
ignored.
A read or write takes place when the TAP controller enters UPDATE-DR state.
•
•
The Debug Comms Control Register is read-only and allows synchronized handshaking
between the processor and the debugger.
•
•
Several commands on the Flash memory are available. These commands are summarized in
Table 21 on page 105. Commands are run by the programmer through the serial interface that
is reading and writing the Debug Comms Registers.
This command is used to read the Flash contents. The memory map is accessible through this
command. Memory is seen as an array of words (32-bit wide). The read command can start at
any valid address in the memory plane. This address must be word-aligned. The address is
automatically incremented.
Table 35. Read Command
4
Read/Write
Write
Write
Read
Read
...
Read
Address
The address of the Debug Comms Control Register is 0x04.
The address of the Debug Comms Data Register is 0x05.
Bit 1 (W): Denotes whether the programmer can read a data through the Debug Comms
Data Register. If the device is busy W = 0, then the programmer must poll until W = 1.
Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms Data
Register. If R = 1, data previously placed there through the scan chain has not been
collected by the device and so the programmer must wait.
Decoder
Address
5
0
31
DR Data
(Number of Words to Read) << 16 | READ
Address
Memory [address]
Memory [address+4]
...
Memory [address+(Number of Words to Read - 1)* 4]
Debug Comms Control Register
Debug Comms Control Register
Data
32
0
6071A–ATARM–28-Oct-04
TDO