AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 311

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Pin Name List
Table 70. I/O Lines Description
Product
Dependencies
I/O Lines
Power
Management
Interrupt
Functional
Description
6071A–ATARM–28-Oct-04
Pin Name
RF
RK
RD
TF
TK
TD
The pins used for interfacing the compliant external devices may be multiplexed with PIO
lines.
Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC
receiver I/O lines to the SSC peripheral mode.
Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC
transmitter I/O lines to the SSC peripheral mode.
The SSC is not continuously clocked. The SSC interface may be clocked through the Power
Management Controller (PMC), therefore the programmer must first configure the PMC to
enable the SSC clock.
The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling interrupts requires programming the AIC before configuring the SSC.
All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each
pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt ser-
vice routine can get the interrupt origin by reading the SSC interrupt status register.
This chapter contains the functional description of the following: SSC Functional Block, Clock
Management, Data format, Start, Transmitter, Receiver and Frame Sync.
The receiver and transmitter operate separately. However, they can work synchronously by
programming the receiver to use the transmit clock and/or to start a data transfer when trans-
mission starts. Alternatively, this can be done by programming the transmitter to use the
receive clock and/or to start a data transfer when reception starts. The transmitter and the
receiver can be programmed to operate with the clock signals provided on either the TK or RK
pins. This allows the SSC to support many slave-mode data transfers. The maximum clock
speed allowed on the TK and RK pins is the master clock divided by 2. Each level of the clock
must be stable for at least two master clock periods.
Pin Description
Receiver Frame Synchro
Receiver Clock
Receiver Data
Transmitter Frame Synchro
Transmitter Clock
Transmitter Data
AT91SAM7S32 Preliminary
Input/Output
Input/Output
Input/Output
Input/Output
Output
Type
Input
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