AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 251

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Functional
Description
Transfer Format
Modes of
Operation
Transmitting Data
6071A–ATARM–28-Oct-04
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte
must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see
Figure 92 on page 251).
Each transfer begins with a START condition and terminates with a STOP condition (see Fig-
ure 91 on page 251).
•
•
Figure 91. START and STOP Conditions
Figure 92. Transfer Format
The TWI has two modes of operation:
•
•
The TWI Control Register (TWI_CR) allows configuration of the interface in Master Mode. In
this mode, it generates the clock according to the value programmed in the Clock Waveform
Generator Register (TWI_CWGR). This register defines the TWCK signal completely,
enabling the interface to be adapted to a wide range of clocks.
After the master initiates a Start condition, it sends a 7-bit slave address, configured in the
Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the
slave address indicates the transfer direction (write or read). If this bit is 0, it indicates a write
operation (transmit operation). If the bit is 1, it indicates a request for data read (receive
operation).
The TWI transfers require the slave to acknowledge each received byte. During the acknowl-
edge clock pulse, the master releases the data line (HIGH), enabling the slave to pull it down
in order to generate the acknowledge. The master polls the data line during this clock pulse
and sets the NAK bit in the status register if the slave does not acknowledge the byte. As with
the other status bits, an interrupt can be generated if enabled in the interrupt enable register
(TWI_IER). After writing in the transmit-holding register (TWI_THR), setting the START bit in
A high-to-low transition on the TWD line while TWCK is high defines the START condition.
A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Master transmitter mode
Master receiver mode
TWD
TWCK
Start
Address
TWCK
TWD
R/W
Start
Ack
AT91SAM7S32 Preliminary
Data
Ack
Data
Stop
Ack
Stop
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