AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 155

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Peripheral Clock
Controller
Programmable
Clock Output
Controller
Programming
Sequence
6071A–ATARM–28-Oct-04
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock,
which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the
product.
When the Processor Clock is disabled, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
The Power Management Controller controls the clocks of each embedded peripheral by the
way of the Peripheral Clock Controller. The user can individually enable and disable the Mas-
ter Clock on the peripherals by writing into the Peripheral Clock Enable (PMC_PCER) and
Peripheral Clock Disable (PMC_PCDR) registers. The status of the peripheral clock activity
can be read in the Peripheral Clock Status Register (PMC_PCSR).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks
are automatically disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the periph-
eral has executed its last programmed operation before disabling the clock. This is to avoid
data corruption or erroneous behavior of the system.
The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and
PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number
corresponds to the interrupt source number assigned to the peripheral.
The PMC controls 3 signals to be output on external pins PCKx. Each signal can be indepen-
dently programmed via the PMC_PCKx registers.
PCKx can be independently selected between the Slow clock, the PLL output and the main
clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a
power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx.
Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of
PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks
are given in the PCKx bits of PMC_SCSR (System Clock Status Register).
Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is
actually what has been programmed in the Programmable Clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching
clocks, it is strongly recommended to disable the Programmable Clock before any configura-
tion change and to re-enable it after the change is actually performed.
1. Enabling the Main Oscillator:
The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register.
In some cases it may be advantageous to define a start-up time. This can be achieved by
writing a value in the OSCOUNT field in the CKGR_MOR register.
Once this register has been correctly configured, the user must wait for MOSCS field in
the PMC_SR register to be set. This can be done either by polling the status register or by
waiting the interrupt line to be raised if the associated interrupt to MOSCS has been
enabled in the PMC_IER register.
Code Example:
Start Up Time = 8 * OSCOUNT / SLCK = 56 Slow Clock Cycles.
write_register(CKGR_MOR,0x00000701)
AT91SAM7S32 Preliminary
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