AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 277

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Parity
6071A–ATARM–28-Oct-04
The USART supports five parity modes selected by programming the PAR field in the Mode
Register (US_MR). The PAR field also enables the Multidrop mode, which is discussed in a
separate paragraph. Even and odd parity bit generation and error detection are supported.
If even parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a
number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly,
the receiver parity checker counts the number of received 1s and reports a parity error if the
sampled parity bit does not correspond. If the odd parity is selected, the parity generator of the
transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1
if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of
received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark
parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters.
The receiver parity checker reports an error if the parity bit is sampled at 0.If the space parity is
used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The
receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the
transmitter does not generate any parity bit and the receiver does not report any parity error.
Table 63 shows an example of the parity bit for the character 0x41 (character ASCII “A”)
depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added
when a parity is odd, or 0 is added when a parity is even. I
Table 63. Parity Bit Examples
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Sta-
tus Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR)
with the RSTSTA bit at 1. Figure 110 illustrates the parity bit status setting and clearing.
Figure 110. Parity Error
Character
A
A
A
A
A
Baud Rate
RXRDY
US_CR
PARE
Clock
Write
RXD
Start
Bit
Hexa
0x41
0x41
0x41
0x41
0x41
D0
D1
D2
D3
AT91SAM7S32 Preliminary
D4
0100 0001
0100 0001
0100 0001
0100 0001
0100 0001
Binary
D5
D6
D7
Parity
Bad
Bit
Stop
Bit
Parity Bit
None
1
0
1
0
RSTSTA = 1
Parity Mode
Space
None
Even
Mark
Odd
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