AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 345

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Capture Operating
Mode
Capture Registers A
and B
Trigger Conditions
6071A–ATARM–28-Oct-04
Regardless of the trigger used, it will be taken into account at the following active edge of the
selected clock. This means that the counter value can be read differently from zero just after a
trigger, especially when a low frequency signal is selected as the clock.
This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register).
Capture Mode allows the TC channel to perform measurements such as pulse timing, fre-
quency, period, duty cycle and phase on TIOA and TIOB signals which are considered as
inputs.
Figure 151 shows the configuration of the TC channel when programmed in Capture Mode.
Registers A and B (RA and RB) are used as capture registers. This means that they can be
loaded with the counter value when a programmable event occurs on the signal TIOA.
The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the
LDRB parameter defines the TIOA edge for the loading of Register B.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since
the last loading of RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag
(LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten.
In addition to the SYNC signal, the software trigger and the RC compare trigger, an external
trigger can be defined.
The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The
ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an exter-
nal trigger. If ETRGEDG = 0 (none), the external trigger is disabled.
AT91SAM7S32 Preliminary
345