AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 21

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Debug Unit
Periodic Interval Timer
Watchdog Timer
Real-time Timer
PIO Controller
Voltage Regulator
Controller
6071A–ATARM–28-Oct-04
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The aim of this controller is to select the Power Mode of the Voltage Regulator between
Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set).
Fast Forcing
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General Interrupt Mask
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Comprises:
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Two-pin UART
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Debug Communication Channel Support
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Chip ID Registers
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20-bit programmable counter plus 12-bit interval counter
12-bit key-protected Programmable Counter running on prescaled SLCK
Provides reset or interrupt signals to the system
Counter may be stopped while the processor is in debug state or in idle mode
32-bit free-running counter with alarm running on prescaled SLCK
Programmable 16-bit prescaler for SLCK accuracy compensation
One PIO Controller, controlling 21 I/O lines
Fully programmable through set/clear registers
Multiplexing of two peripheral functions per I/O line
For each I/O line (whether assigned to a peripheral or used as general-purpose I/O)
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Synchronous output, provides Set and Clear of several I/O lines in a single write
Permits redirecting any interrupt source on the fast interrupt
Provides processor synchronization on events without triggering an interrupt
One two-pin UART
One Interface for the Debug Communication Channel (DCC) support
One set of Chip ID Registers
One interface providing ICE Access Prevention
Implemented features are compatible with the USART
Programmable Baud Rate Generator
Parity, Framing and Overrun Error
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Offers visibility of COMMRX and COMMTX signals from the ARM Processor
Identification of the device revision, sizes of the embedded memories, set of
peripherals
Chip ID is 0x27080340 (VERSION 0)
Input change interrupt
Half a clock period glitch filter
Multi-drive option enables driving in open drain
Programmable pull-up on each I/O line
Pin data status register, supplies visibility of the level on the pin at any time
AT91SAM7S32 Preliminary
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