AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 49
AT91SAM7S32-AI
Manufacturer Part Number
AT91SAM7S32-AI
Description
AT91 ARM Thumb-based Microcontrollers
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT91SAM7S32-AI.pdf
(446 pages)
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Reset State
Priorities
Reset Controller
Status Register
6071A–ATARM–28-Oct-04
The Reset State Manager manages the following priorities between the different reset
sources, given in descending order:
•
•
•
•
•
Particular cases are listed below:
•
•
•
The Reset Controller status register (RSTC_SR) provides several status fields:
•
•
•
•
•
Power-up Reset
Brownout Reset
Watchdog Reset
Software Reset
User Reset
When in User Reset:
–
–
When in Software Reset:
–
–
When in Watchdog Reset:
–
–
RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
SRCMP bit: This field indicates that a Software Reset Command is in progress and that no
further software reset should be performed until the end of the current one. This bit is
automatically cleared at the end of the current software reset.
NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled
on each MCK rising edge.
URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR
register. This transition is also detected on the Master Clock (MCK) rising edge (see
Figure 21). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled
by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt.
Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt.
BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled
(bod_rst_en = 0). It triggers an interrupt if the bit BODIEN in the RSTC_MR register
enables the interrupt. Reading the RSTC_SR register resets the BODSTS bit and clears
the interrupt.
A watchdog event is impossible because the Watchdog Timer is being reset by the
proc_nreset signal.
A software reset is impossible, since the processor reset is being activated.
A watchdog event has priority over the current state.
The NRST has no effect.
The processor reset is active and so a Software Reset cannot be programmed.
A User Reset cannot be entered.
AT91SAM7S32 Preliminary
49
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