AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 175

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Product
Dependencies
I/O Lines
Power
Management
Interrupt Source
UART
Operations
Baud Rate
Generator
6071A–ATARM–28-Oct-04
Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In
this case, the programmer must first configure the corresponding PIO Controller to enable I/O
lines operations of the Debug Unit.
Depending on product integration, the Debug Unit clock may be controllable through the
Power Management Controller. In this case, the programmer must first configure the PMC to
enable the Debug Unit clock. Usually, the peripheral identifier used for this purpose is 1.
Depending on product integration, the Debug Unit interrupt line is connected to one of the
interrupt sources of the Advanced Interrupt Controller. Interrupt handling requires program-
ming of the AIC before configuring the Debug Unit. Usually, the Debug Unit interrupt line
connects to the interrupt source 1 of the AIC, which may be shared with the real-time clock,
the system timer interrupt lines and other system peripheral interrupts, as shown in Figure 62.
This sharing requires the programmer to determine the source of the interrupt when the
source 1 is triggered.
The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit char-
acter handling (with parity). It has no clock pin.
The Debug Unit's UART is made up of a receiver and a transmitter that operate independently,
and a common baud rate generator. Receiver timeout and transmitter time guard are not
implemented. However, all the implemented features are compatible with those of a standard
USART.
The baud rate generator provides the bit period clock named baud rate clock to both the
receiver and the transmitter.
The baud rate clock is the master clock divided by 16 times the value (CD) written in
DBGU_BRGR (Baud Rate Generator Register). If DBGU_BRGR is set to 0, the baud rate
clock is disabled and the Debug Unit's UART remains inactive. The maximum allowable baud
rate is Master Clock divided by 16. The minimum allowable baud rate is Master Clock divided
by (16 x 65536).
Figure 64. Baud Rate Generator
MCK
16-bit Counter
CD
Baud Rate
AT91SAM7S32 Preliminary
OUT
0
=
-------------------- -
16
CD
>1
1
0
MCK
CD
Divide
by 16
Baud Rate
Receiver
Sampling Clock
Clock
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