AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 158

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Clock Switching Details
Master Clock
Switching Timings
158
AT91SAM7S32 Preliminary
Note:
Table 47 gives the worst case timing required for the Master Clock to switch from one selected
clock to another one. This is in the event that the prescaler is de-activated. When the prescaler
is activated, an additional time of 64 clock cycles of the new selected clock has to be added.
Table 47. Clock Switching Timings (Worst Case)
To
Main Clock
SLCK
PLL Clock
Depending on the system used, 8 peripheral clocks can be enabled or disabled. The
PMC_PCSR provides a clear view as to which peripheral clock is enabled.
Code Examples:
write_register(PMC_PCER,0x00000110)
Peripheral clocks 4 and 8 are enabled.
write_register(PMC_PCDR,0x00000010)
Peripheral clock 4 is disabled.
Each enabled peripheral clock corresponds to Master Clock.
From
PLLCOUNT x SLCK +
0.5 x Main Clock +
0.5 x Main Clock +
2.5 x PLLx Clock
Main Clock
4 x SLCK +
4.5 x SLCK
–
PLLCOUNT x SLCK
2.5 x PLL Clock +
2.5 x Main Clock
4 x SLCK +
5 x SLCK +
SLCK
–
PLLCOUNT x SLCK
2.5 x PLL Clock +
3 x PLL Clock +
3 x PLL Clock +
1 x Main Clock
6071A–ATARM–28-Oct-04
4 x SLCK +
4 x SLCK +
PLL Clock
5 x SLCK