AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 357
AT91SAM7S32-AI
Manufacturer Part Number
AT91SAM7S32-AI
Description
AT91 ARM Thumb-based Microcontrollers
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT91SAM7S32-AI.pdf
(446 pages)
- Current page: 357 of 446
- Download datasheet (3Mb)
TC Channel Mode Register: Capture Mode
Register Name: TC_CMR
Access Type:
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• LDBSTOP: Counter Clock Stopped with RB Loading
0 = Counter clock is not stopped when RB loading occurs.
1 = Counter clock is stopped when RB loading occurs.
• LDBDIS: Counter Clock Disable with RB Loading
0 = Counter clock is not disabled when RB loading occurs.
1 = Counter clock is disabled when RB loading occurs.
6071A–ATARM–28-Oct-04
WAVE = 0
LDBDIS
31
23
15
–
–
7
0
0
1
1
0
0
0
0
1
1
1
1
BURST
Read/Write
LDBSTOP
CPCTRG
30
22
14
–
–
6
TCCLKS
0
1
0
1
0
0
1
1
0
0
1
1
The clock is not gated by an external signal.
XC0 is ANDed with the selected clock.
XC1 is ANDed with the selected clock.
XC2 is ANDed with the selected clock.
29
21
13
–
–
–
5
BURST
0
1
0
1
0
1
0
1
28
20
12
–
–
–
4
Clock Selected
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
CLKI
27
19
11
–
–
3
AT91SAM7S32 Preliminary
LDRB
ABETRG
26
18
10
–
2
TCCLKS
25
17
–
1
9
ETRGEDG
LDRA
24
16
–
8
0
357
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